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d a t a sh eet product speci?cation file under integrated circuits, ic01 september 1991 integrated circuits TDA1547 dual top-performance bitstream dac
september 1991 2 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 features top-grade audio performance C very low harmonic distortion C high signal-to-noise ratio C wide dynamic range of approximately 108 db (not a-weighted) high crosstalk immunity bitstream concept C high over-sampling rate up to 192 f s C pulse-density modulation C inherently monotonic C no zero-crossing distortion general description the TDA1547 is a dedicated one-bit digital-to-analog converter to facilitate a high fidelity sound reproduction of digital audio. the TDA1547 is extremely suitable for use in high quality audio systems such as compact disc and dat players, or in digital amplifiers and digital signal processing systems. the TDA1547 is used in combination with the saa7350 bitstream circuit, which includes the third-order noise shaper. the excellent performance of the saa7350 and TDA1547 bitstream conversion system is obtained by separating the noise shaping circuit and the one-bit conversion circuit over two ic's, thereby reducing the crosstalk between the digital and analog parts. the TDA1547 one-bit converter is processed in bimos. in the digital logic and drivers bipolar transistors are used to optimize speed and to reduce digital noise generation. in the analog part the bipolar transistors are used to obtain high performance of the operational amplifiers. special layout precautions have been taken to achieve a high crosstalk immunity. the layout of the TDA1547 has fully separated left and right channels and supply voltage lines between the digital and analog sections. ordering information note 1. sot-232-1; 1996 august 23. extended type number package pins pin position material code TDA1547 (1) 32 sdil plastic sot232a
september 1991 3 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 fig.1 pinning diagram. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 17 18 19 20 21 22 23 24 25 26 mcd294 dgnd v ddd in r n.c. n.c. clk r v ddd r v ssd r v ref r v ssa ?dac r + dac r agnd r + out r ?out r TDA1547 v ssd in l n.c. n.c. clk l v ddd l v ssd l v ref l v dda ?dac l + dac l agnd l + out l ?out l v sub agnd dac r agnd dac l
september 1991 4 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 pinning symbol pin description dgnd 1 0 v digital supply v ddd 2 5 v digital supply for both channels in r 3 serial one-bit data input for the right channel n.c. 4 pin not connected; should preferably be connected to digital ground clk r 5 clock input for the right channel v ddd r 6 5 v digital supply for the right channel; this voltage determines the internal logic high level in the right channel v ssd r 7 - 3.5 v digital supply for the right channel; this voltage determines the internal logic low level in the right channel v ref r 8 - 4 v reference voltage for the right channel switched capacitor dac agnd dac r 9 0 v reference voltage for the right channel switched capacitor dac; this pin should be connected to analog ground - dac r 10 output from the right negative switched capacitor dac; feedback connection for the right negative operational ampli?er +dac r 11 output from the right positive switched capacitor dac; feedback connection for the right positive operational ampli?er agnd r 12 0 v reference voltage for both right channel operational ampli?ers n.c. 13 pin not connected; should preferably be connected to analog ground +out r 14 + output of the switched capacitor operational ampli?er - out r 15 - output of the switched capacitor operational ampli?er v ssa 16 - 5 v analog supply v dda 17 5 v analog supply - out l 18 - output of the switched capacitor operational ampli?er +out l 19 + output of the switched capacitor operational ampli?er n.c. 20 pin not connected; should preferably be connected to analog ground agnd l 21 0 v reference voltage for both left channel operational ampli?ers +dac l 22 output from the left positive switched capacitor dac; feedback connection for the left positive operational ampli?er - dac l 23 output from the left negative switched capacitor dac; feedback connection for left negative operational ampli?er agnd dac l 24 0 v reference voltage for the left channel switched capacitor dac; this pin should be connected to analog ground v ref l 25 - 4 v reference voltage for the left channel switched capacitor dac v ssd l 26 - 3.5 v digital supply for the left channel; this voltage determines the internal logic low level in the left channel v ddd l 27 5 v digital supply for the left channel; this voltage determines the internal logic high level in the left channel
september 1991 5 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 quick reference data clk l 28 clock input for the left channel n.c. 29 pin not connected; should preferably be connected to digital ground in l 30 serial one-bit data input for the left channel v ssd 31 - 5 v digital supply for both channels v sub 32 - 5 v substrate voltage symbol parameter condition min typ max unit supply voltages v ddd l. r positive digital supply voltage for one channel; pins 27 and 6 4.5 5.0 5.5 v v ddd digital supply voltage for both channels; pin 2 4.5 5.0 5.5 v v ssd l. r negative digital supply voltage for one channel; pins 26 and 7 - 4.0 - 3.5 - 3.0 v v ssd negative digital supply voltage for both channels; pin 31 - 5.5 - 5.0 - 4.5 v v dda positive analog supply voltage; pin 17 4.5 5.0 6 v v ssa negative analog supply voltage; pin 16 - 6.0 - 5.0 - 4.5 v supply current i ddd l. r positive digital supply current for one channel; pins 27 and 6 - 0.1 - ma i ddd digital supply current for both channels; pin 2 - 29.0 - ma i ssd l. r negative digital supply current for one channel; pins 26 and 7 -- 0.1 - ma i ssd negative supply current for both channels; pin 31 -- 28.0 - ma i dda positive analog supply current; pin 17 - 51.0 - ma i ssa negative analog supply current; pin 16 -- 51.0 - ma p tot total power dissipation - 800 - mw v out(rms) output voltage (rms value) f clk = 8.46 mhz; notes 1 and 2 0.85 1.0 1.15 v symbol pin description
september 1991 6 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 notes to the quick reference data 1. output level tracks linearly with both the clock frequency and the reference voltage (v ref l or v ref r ). 2. device measured in differential mode with external components as shown in fig.5. 3. measured with a one-bit data signal generated by the saa7350 from an 8 f s (352.8 khz), 20-bit, 1 khz digital sinewave. measured over a 20 hz to 20 khz bandwidth. 4. measured with a one-bit data signal generated by the saa7350 from an 8 f s (352.8 khz), 20-bit, 20 hz to 20 khz digital sinewave. measured over a 20 hz to 20 khz bandwidth. 5. the specified signal-to-noise ratio includes noise introduced by the application components as shown in fig.5. functional description both channels are completely separated to reach the desired high crosstalk suppression level. each channel consists of the following functional parts: thermal resistance supply current (thd + n)/s thd + noise; 0 db 1 khz; notes 2 and 3 -- 101 - 96 db - 0.0009 0.0016 % (thd + n)/s thd + noise; 0 db f = 20 hz to 20 khz; -- 101 - db notes 2 and 4 - 0.0009 - % (thd + n)/s thd + noise; - 20 db f = 1 khz; notes 2 and 3 -- 88 - 84 db (thd + n)/s thd + noise; - 60 db f = 1 khz; notes 2 and 3 -- 48 - 44 db s/n signal-to-noise ratio pattern 0101..; notes 2 and 5 109 111 - db s/n signal-to-noise ratio; a-weighting pattern 0101..; notes 2 and 5 - 113 - db f clk maximum clock frequency -- 10 mhz a channel separation f = 1 khz 101 115 - db t amb operating ambient temperature - 20 - 70 c - one-bit input, which latches the incoming data to the system clock. - switch driver circuit, which generates the non-overlapping clock- and data-signals that control the dac switched capacitor networks. - switched capacitor network, this forms the actual dac function, it supplies charge packets to the low-pass ?lter, under control of the incoming one-bit code. - two high performance operational ampli?ers, that perform the charge packet to voltage conversion and deliver a differential output signal. the ?rst pole of the low-pass ?lter is built around them. symbol parameter max. unit r th j-a from junction to ambient 60 k/w symbol parameter condition min typ max unit
september 1991 7 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 handbook, full pagewidth mcd293 data input right clock input right n.c. data input left n.c. clock input left v sub switched capacitor network switch drivers one-bit input 29 28 32 26 23 20 19 31 25 22 18 30 27 24 21 17 n.c. n.c. switched capacitor network switch drivers one-bit input 45 1 7 10 13 14 2 8 11 15 36912 16 TDA1547 dgnd (0 v) v ddd (+5 v) v ssd r (?3.5 v) v ref r (?4 v) v ssa (?5 v) agnd dac r (0 v) v ddd r (+5 v) agnd r (0 v) (?5 v) v ssd (?5 v) v ddd l (+5 v) v dda (+5 v) v ref l (?4 ) v ssd l (?3.5 v) (0 v) agnd l (0 v) left channel right channel negative dac output positive dac output positive output negative output negative dac output positive dac output agnd dac l positive output negative output fig.2 block diagram.
september 1991 8 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 limiting values in accordance with the absolute maximum system (iec 134) notes to the limiting values 1. the substrate voltage must be lower than or equal to the lowest supply voltage. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. symbol parameter conditions min max. unit v sub negative substrate voltage; pin 32 note 1 - 7.0 - v v ddd l. r positive digital supply voltage; pins 27 and 6 - 5.5 v v ddd positive digital supply voltage; pin 2 - 5.5 v v ssd l. r negative digital supply voltage; pins 26 and 7 - 4.0 - v v ssd negative digital supply voltage; pin 31 - 5.5 - v v dda positive analog supply voltage; pin 17 - 6.0 v v ssa negative analog supply voltage; pin 16 - 6.0 - v v ddd l. r - v ssd l. r supply voltage difference between pins 27, 6 and pins 26, 7 - 9.0 v p tot total power dissipation t amb = 70 c - 1300 mw v ref l. r input reference voltage; pins 25 and 8 - 6.0 v v clk l. r input voltage clock; pins 28 and 5 - 0.5 v ddd +0.5 v v i l input voltage channel; pin 30 - 0.5 v ddd +0.5 v v i r input voltage channel; pin 3 - 0.5 v ddd +0.5 v t amb operating ambient temperature - 20 70 c t stg storage temperature - 40 150 c t xtal maximum crystal temperature - 150 c v es electrostatic handling note 2 - 2000 v
september 1991 9 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 characteristics v ddd , v ddd l. r , v dda = +5 v; v ssd , v ssa = - 5 v, v ssd l. r = - 3.5 v; v ref l. r = - 4 v; t amb = 25 c; f clk = 8.46 mhz; unless otherwise speci?ed symbol parameter conditions min typ max unit supply v sub negative substrate voltage; pin 32 note 1 - 7.0 -- 4.5 v v ddd l. r positive digital supply voltage for one channel; pins 27 and 6 4.5 5.0 5.5 v v ddd digital supply voltage for both channels; pin 2 4.5 5.0 5.5 v v ssd l. r negative digital supply voltage for one channel; pins 26 and 7 - 4.0 - 3.5 - 3.0 v v ssd negative digital supply voltage for both channels; pin 31 - 5.5 - 5.0 - 4.5 v v dda positive analog supply voltage; pin 17 4.5 5.0 6.0 v v ssa negative analog supply voltage; pin 16 - 6.0 - 5.0 - 4.5 v v ddd l. r - v ssd l, r supply voltage difference between pins 27, 6 and pins 26, 7 -- 9.0 v v ssd l. r - v ssd supply voltage difference between pins 26, 7 and pin 31 1.3 -- v i ddd l. r positive digital supply current for one channel; pins 27 and 6 - 0.1 - ma i ddd digital supply current for both channels; pin 2 29.0 46 ma i ssd l. r negative digital supply current for one channel; pins 26 and 7 -- 0.1 - ma i ssd negative supply current for both channels; pin 31 - 45 - 28.0 - ma - i dda positive analog supply current; pin 17 - 51.0 63 ma i ssa negative analog supply current; pin 16 - 63.0 - 51.0 - ma p ssr1 power supply rejection ratio v ddd l, r ; note 6 50 -- db p ssr2 power supply rejection ratio v ddd ; note 6 50 -- db p ssr3 power supply rejection ratio v ssd l, r ; note 6 60 -- db p ssr4 power supply rejection ratio v ssd ; note 6 50 -- db p ssr5 power supply rejection ratio v dda ; note 6 60 -- db p ssr6 power supply rejection ratio v ssa ; note 6 60 -- db p tot total power dissipation - 800 - mw clock - input v il input voltage low -- 0.5 v v ih input voltage high 4.5 -- v i il input current low v i = 0.5 v - 10 - 10 m a
september 1991 10 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 i ih input current high v i = 4.5 v - 10 - 10 m a c i clock input capacitance - 5 - pf f clk clock input frequency -- 10 mhz channel left/right inputs v il input voltage low -- 0.5 v v ih input voltage high - 4.5 - v i il input current low v i = 0.5 v - 10 - 10 m a i ih input current high v i = 4.5 v - 10 - 10 m a c i channel input capacitance; pins 3, 30 - 5 - pf v ref reference input voltage; pins 8, 25 note 2 -- 4 0.4 - v audio outputs v out(rms) output voltage (rms value); pins 14, 19; pins 15, 18 notes 2 and 3 0.85 1.0 1.15 v (thd + n)/s thd + noise; 0 db f = 1 khz; -- 101 - 96 db notes 3 and 4 - 0.0009 0.0016 % (thd + n)/s thd + noise; 0 db 20 hz - 20 khz; -- 101 - db notes 3 and 5 - 0.0009 - % (thd + n)/s thd + noise; - 20 db f = 1 khz; notes 3 and 4 -- 88 - 84 db (thd + n)/s thd + noise; - 60 db f = 1 khz; notes 3 and 4 -- 48 - 44 db s/n signal-to-noise ratio pattern 0101; notes 3 and 7 109 111 - db s/n signal-to-noise ratio; a-weighting pattern 0101; notes 3 and 7 - 113 - db a channel separation f = 1 khz 101 115 - db timing t r rise time clock input c l = 20 pf - 510ns t f fall time clock input c l = 20 pf - 510ns t clk l clock input low time 45 -- ns t clk h clock input high time 45 -- ns t r channel input rise time c l = 20 pf - 10 15 ns t f channel input fall time c l = 20 pf - 10 15 ns t hd channel input hold time 25 -- ns t su channel input set-up time 0 -- ns symbol parameter conditions min typ max unit
september 1991 11 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 notes to the characteristics 1. the substrate voltage must be lower than or to equal than the lowest supply voltage. 2. output level tracks linearly with both the clock frequency and the reference voltage (v ref l or v ref r ). 3. device measured in differential mode with external components as shown in fig.5. 4. measured with a one-bit data signal generated by the saa7350 from an 8 f s (352.8 khz), 20-bit, 1 khz digital sinewave. measured over a 20 hz to 20 khz bandwidth. 5. measured with a one-bit data signal generated by the saa7350 from an 8 f s (352.8 khz), 20-bit, 20 hz to 20 khz digital sinewave. measured over a 20 hz to 20 khz bandwidth. 6. power supply rejection ratio measured with f ripple = 1 khz and v ripple = 100 mv. 7. the specified signal-to-noise ratio includes noise introduced by the application components as shown in fig.5. timing handbook, full pagewidth mcd295 t clk h t r t clk l t f v ddd ?1.0 v 1.0 v v il v ih clk v ddd ?1.0 v 1.0 v v il v ih t su t hd data input channel l, channel r v il data stable fig.3 timing waveform.
september 1991 12 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 application information l channel r channel 8 x upsampling digital filter, astop > 110 db 24 x upsampling by zero-order hold, 3rd order noise shaping, 1-bit end quantization 1-bit high-performance dac converter 3rd order analog postfilter, f = 55 khz butterworth response o 16-bit audio data, f = 44.1 khz s 20-bit, f = 352.8 khz s 1-bit, f = 8.47 mhz s TDA1547 saa7350 digital filter mcd296 system clock f = 16.9 mhz system clock f = 16.9 mhz fig.4 cd-range bitstream reconstruction system (192 f s over-sampling).
september 1991 13 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 handbook, full pagewidth saa7350 3 4 5 7 8 9 10 42 43 44 digital filter interface inputs input data mode select 1-bit dac interface outputs dol clk dor bitclock wordclock data left data right idf3 = high idf2 = high idf1 = low stereo 1-bit data to TDA1547 sony or npc 8 x f simultaneous mode 20-bit input format mcd297 TDA1547 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 17 18 19 20 21 22 23 24 25 26 right channel left channel switched capacitor network switched capacitor network logic and drivers logic and drivers to analog output stage to analog output stage + 5 v (analog) ?5 v (analog) c 220 f 3.3 k 560 ?5 v (analog) c 3.3 k 1.5 k ?5 v (digital) 10 + 5 v (digital) c dol clk l ?5 v (digital) 10 c ?5 v (digital) 10 c c 220 f 3.3 k 560 ?5 v (analog) c 3.3 k 1.5 k ?5 v (digital) 10 + 5 v (digital) c dor clk r + 5 v (digital) 10 c c 4.7 c 4.7 c = 100 nf (chip capacitor) s scki wsi sdi1 sdi2 x sys 2 (in l) (in r) fig.5 application diagram.
september 1991 14 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 handbook, full pagewidth 1-bit dac left 1-bit dac right 23 19 22 18 21 10 14 11 15 12 820 pf 13 k 220 pf 13 k 220 pf 820 pf 13 k 220 pf 13 k 220 pf 2.61 k 2.2 nf 100 h 100 f 3.3 k 10 k 10 k 56 pf 3.3 k 1 k 470 33 nf 3.3 nf 560 pf 1.62 k 1.5 k 47 de-emphasis kill audio output right 2.61 k 2.2 nf 100 h 100 f 3.3 k 10 k 10 k 56 pf 3.3 k 1 k 470 33 nf 3.3 nf 560 pf 1.62 k 1.5 k 47 de-emphasis kill audio output left TDA1547 mcd298 fig.6 post-filter for 192 f s application (f 0 = 55 khz).
september 1991 15 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 note: graph constructed from average measurements values of a small amount of engineering samples. no guarantee for typical values is implied. handbook, full pagewidth mcd299 1 khz 10 hz ?80 ?100 ?120 (thd + n) / s (db) 10 khz 100 hz 100 khz (%) 0.01 0.001 0.0001 (thd + n) / s signal f level =0 db fig.7 (thd + n)/s as a function of signal frequency. note: graph constructed from average measurement values of a small amount of engineering samples. no guarantee for typical values is implied. fig.8 (thd + n)/s as a function of test signal level. handbook, halfpage ?100 ?40 0 ?110 ?10 ?30 mcd300 ?90 ?70 ?50 ?80 ?20 ?60 (thd + n) / s (db) signal level (db)
september 1991 16 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 note: graph constructed from average measurements values of a small amount of engineering samples. no guarantee for typical values is implied. handbook, full pagewidth mcd301 1 khz 10 hz ?115 ?120 ?125 ?130 crosstalk (db) 10 khz 100 hz 100 khz rl lr test signal f fig.9 inter-channel crosstalk as a function of signal frequency.
september 1991 17 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot232-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 32 1 17 16 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip32: plastic shrink dual in-line package; 32 leads (400 mil) sot232-1
september 1991 18 philips semiconductors product speci?cation dual top-performance bitstream dac TDA1547 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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